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Writing about user experience design practice, career development, and evolving approaches to digital products.

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Fixed-Point Arithmetic in Verilog: A Beginner’s Guide to Representing Fractions in Hardware

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Day 36: Shift Registers — Why Does the Bit Order Look Reversed?

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Day 34: Parameterized Counters — Why Does a Width of One Break My Design?

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Who to follow

Popular this week

csjo logicion

Fixed-Point Arithmetic in Verilog: A Beginner’s Guide to Representing Fractions in Hardware

csjo logicion

Round-Robin Arbiters in Verilog: A Beginner’s Guide to Fair Resource Sharing

csjo logicion

The FPGA Design Flow Explained: From RTL to Bitstream

csjo logicion

Building a Multiplier in Verilog: A Beginner’s Guide to Shift-and-Add

csjo logicion

Moore vs Mealy State Machines in Verilog: A Beginner’s Guide to Choosing the Right FSM Style

Latest stories

BRUNDA RAJ G K

Day 36: Shift Registers — Why Does the Bit Order Look Reversed?

BRUNDA RAJ G K

Day 35: Clock Enable — Why Is My Register Updating One Cycle Late?

BRUNDA RAJ G K

Day 34: Parameterized Counters — Why Does a Width of One Break My Design?

BRUNDA RAJ G K

Day 33: Up/Down Counters — What Happens at Zero and Maximum Count?

Jaja Requa

I GAVE MY TEACHER AN F. — THE SCREENSHOTS DON’T LIE | PART 2

See more stories

Who to follow