wuhuajin·Oct 15Can AI Write Verilog for FPGAs# Can AI Actually Write Verilog for FPGAs? My Real-World Test
Muhammad Ibrahim·Oct 1Building a 3-Digit Up/Down BCD Counter on the Nexys A7 FPGA in VerilogDesigning hardware on an FPGA means bridging the gap between a 100 MHz silicon clock and human-readable outputs. In this tutorial, we build…
Lesile Guo·Sep 24AD9253 on a Production Board? A Practical Second-Source Evaluation for Quad ADCsHow to check a pin-to-pin option without losing sight of FPGA capture and product qualification.
Noah Bean·Sep 18Altera’s IPO Is an AI Pitch Built on a Forty-Year-Old Tradeoff in SiliconThe FPGA pioneer is heading back to public markets after a decade inside Intel. To value it, start with routing multiplexers, mask costs…
Stephan Bökelmann·May 14Zero to One: VHDL and a Lattice iCEstickThis post is the first in a series on FPGA development with open-source tools. By the end you will have blinked an LED on real hardware…
csjo logicion·Apr 15Top 5 FPGA Boards for Beginners in 2026A Practical Guide to Choosing Your First FPGA Development Board
Ampheo·Dec 29, 2025Why in my FPGA designs always output registers have the highest delays?That’s a super common timing-report “gotcha” in FPGA flows: paths ending at output registers (or output ports) often look worst because…
Abdul Moiz·Nov 25, 2025Designing a Multicycle RISC-V Processor Datapath on Artix-7 FPGA | Part 1: Architectural Overview &…Breaking down the multicycle RISC-V datapath, its instruction stages, and the core modules that form our processor’s foundation.
Iqrajawad·Nov 23, 2025Design and Synthesis of the RV32I Datapath in Verilog (Vivado)Building a CPU might sound scary at first, but it’s actually a lot like putting together a LEGO set — one block at a time. While working…
