Jaivardhangjain·Oct 30Introduction to the PD Flow and PartitioningThis is the first blog in a series that walks through the entire Physical Design Flow in detail. The Physical Design Flow can be divided…
Sktbttr·Oct 20Beyond Physical Design: Understanding Akeana and Its RISC-V Compute Platform (3)Author: Shaik Thouheed Email : sktbttr@gmail.com
Sktbttr·Oct 19From Physical Design to System Architecture: Understanding Ventana’s Veyron RISC-V CPU (2)Autho: Shaik Thouheed sktbttr@gmail.com
Leelavathirajana·Oct 3So if the clock period is correct, why can a design still have a setup timing violation?The answer becomes clearer when I stop looking at the clock period alone and look at the complete timing path.
MosChip®·Sep 24PoV on Top Considerations for Designing AI Inference ChipsAI inference workloads are becoming more compute-intensive, with higher demands on throughput, memory access, and power efficiency.
