Nehanaumankhan·Feb 23RV32I Single-Cycle Processor: Designing and Verifying the Instruction Fetch StageIn this article, we’ll explore how instructions are fetched in a RISCV processor. We will look into the HDL implementation of different…
Abdul Moiz·Nov 25, 2025Designing a Multicycle RISC-V Processor Datapath on Artix-7 FPGA | Part 1: Architectural Overview &…Breaking down the multicycle RISC-V datapath, its instruction stages, and the core modules that form our processor’s foundation.
Nehanaumankhan·Nov 24, 2025RISC-V Single-Cycle Processor Datapath Design (SCDP)In this article, we will focus on understanding the RV32I single-cycle datapath (SCDP) and its core components.
Ruban S·Jun 14, 2025Superscaling and Superpipelining: The Difference between a Processor and a Super Processor“The bigger the better”; something common for both food and CPU pipelines.
Ruban S·Apr 27, 2025Branch Prediction: The silent clairvoyant living inside the processorA short dive into the world of branch prediction, where they’re used, and why they matter.
Hardwireunicorn·Jan 19, 2025The Smallest Cell of Modern TechnologyHow the Tiny Transistor Powers the Digital RevolutionA response icon2A response icon2
Ruban S·Dec 15, 2024Control HazardsControl Hazards are another type of hazard that can have disastrous effects when not rectified. But to understand why so, we first need to…
Ruban S·Nov 30, 2024Mitigating Data Hazards in the PipelineResolving RAW dependencies in the pipeline
The Arch Bytes: From Core to Code·Nov 12, 2024Load Store Queue: C++ implementation (#2)In last pot, we looked at few structs which are used in the code. Let’s look at the structs related to entry. There are different entries…
The Arch Bytes: From Core to Code·Nov 9, 2024Online resources for Load-Store QueueBefore we move to C++ implementation, let me share some resources for learning about theory. There are some great resources online from…
