Computer Architecture

Embedded Systems

Computer Science

Risc V

Explore recommended reads, summarized by AI

Technical Implementation

Guides and explorations of RISC-V architecture, instruction sets, and development challenges.

Architecture and Design

Game Engine Scripting

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Sumit Verma

Qwenputer: How an AI Model Can Run Its Own CPU and RAM

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Risk-V Emulator in C: Development from Scratch

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Deconstructing the ecall: From C User-Space to RISC-V Bare Metal

Allen Kuo (kwyshell)

Edge Inference Engine: One Native API Across CPU, GPU, NPU, and RISC-V

Muhammad Rizwan

The Hard Part of Writing a RISC-V Assembler Isn’t Parsing Assembly

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Jakub Jirak

RISC-V and the Open Architecture Moment in AI Chips

AI Engineering

QwenPU: Compiling an Entire Working Computer Directly Into LLM Model Weights

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Qwenputer: How an AI Model Can Run Its Own CPU and RAM

Sean Galloway

When Should a DMA’s FSM Become a Processor?

Alpinum Consulting

Published in Electronics World: The Growing Role of Formal Verification in RISC-V Design

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Who to follow

Popular this week

Sumit Verma

Qwenputer: How an AI Model Can Run Its Own CPU and RAM

Zodiac Hacker

Risk-V Emulator in C: Development from Scratch

Jadhavdhananjay

Deconstructing the ecall: From C User-Space to RISC-V Bare Metal

Allen Kuo (kwyshell)

Edge Inference Engine: One Native API Across CPU, GPU, NPU, and RISC-V

Muhammad Rizwan

The Hard Part of Writing a RISC-V Assembler Isn’t Parsing Assembly

Latest stories

Jakub Jirak

RISC-V and the Open Architecture Moment in AI Chips

AI Engineering

QwenPU: Compiling an Entire Working Computer Directly Into LLM Model Weights

Sumit Verma

Qwenputer: How an AI Model Can Run Its Own CPU and RAM

Sean Galloway

When Should a DMA’s FSM Become a Processor?

Alpinum Consulting

Published in Electronics World: The Growing Role of Formal Verification in RISC-V Design

See more stories

Who to follow