lulu2k2·Aug 11SV Assertions Chapter 002Let’s continue with writing some basic assertions. You can write them in different forms. We will discuss each one and why to use them in…
lulu2k2·Aug 4SV Assertions Intro Chapter-001We will see why we need to write assertions and how it makes our verification very easy. We will also see some downsides of it.
lulu2k2·Jun 28UVM tutorial for beginners (Part 001)I will be starting a UVM tutorial series that covers why something is written as it is. We will slowly build up on some core concepts of…
Arvind Soni·May 19Why do we have do_copy(), do_compare() etcOne of the most confusing concepts for beginners in UVM:
Priyadarshinijena·Apr 14VLSI Verification vs Software Testing: A Comparative Analysis of Validation Frameworks and…In modern system design, validation plays a pivotal role in ensuring correctness, reliability, and performance. While software testing has…
Arvind Soni·Apr 8UVM Phases — Complete Reference Guide:Every concept, every phase, the full simulation timeline
Anna Ravitzki·Nov 5, 2025Constructing a Visual Intelligence That Detects Bugs Before Engineers Doby Anna Ravitzki, Inventor of Cogita PROA response icon2A response icon2
semionics·Nov 5, 2025UVM Explanation: Understanding Universal Verification Methodology in Semiconductor VerificationIn the complex world of semiconductor design, ensuring that chips function correctly before manufacturing is crucial. As designs grew from…
semionics·Oct 25, 2025The Unsung Hero of Chip Design: A Deep Dive into VLSI Physical VerificationYou’ve just finished the monumental task of designing a complex System-on-Chip (SoC). The RTL is written, synthesized, and meticulously…
semionics·Oct 8, 2025The Great Refurbishment: How Second-Hand Tech is Challenging Our Obsession with NewnessThere’s a particular ceremony to unboxing a new device. The pristine packaging, the flawless screen, the satisfying peel of protective…
