DXIL Parity Push: 104 golden diff=0, 54.5% line parity
Crossed 100 diff=0 and 50% parity milestones. +10 diff=0 shaders, +6.4pp parity.
New optimizations
| Optimization |
Impact |
| Per-member loadInput DCE |
Backwards reachability eliminates unused struct input loads |
| Zero-store local promotion |
Unassigned struct members → zero constants |
| QuantizeF16 legacy ops |
legacyF32ToF16/F16ToF32, eliminates NativeLowPrecision cascade (13 shaders) |
| Same-type cast elimination |
bitcast i32↔i32 is no-op |
| Strength reduction |
sub X,C→add X,-C, mul X,2^N→shl X,N |
Bug fixes
| Fix |
Root cause |
| Input sigId |
Element index, not register row — broke packed inputs |
| ViewID StartCol |
Packed linear indexing missing column offset |
| Cross-arg struct ordering |
Reverse signature order globally |
| Int64 flag |
Scanned from emitted bitcode, not IR types |
| createHandle |
Always opcode 57, removed dead createHandleFromBinding |
| MSVC groupshared names |
\01?name@@3typeA decoration |
Metrics
| Metric |
v0.17.8 |
v0.17.9 |
| DXC golden diff=0 |
94 |
104 (+10) |
| Line parity |
48.1% |
54.5% (+6.4pp) |
| IDxcValidator |
161/170 |
161/170 |
Note: DXIL backend is experimental.
